1. Field of the Invention
The present invention relates to a multiplier which may suitably apply to processing data such as image data, data from a communication signal or fonts used in a laser printer. More particularly it relates to a multiplier which may process multi-valued signals such as binary signals or quadruple signals.
2. Background of the Related Art
In general, it is known that a multiplier is one kind of arithmetic and logic unit used in an electronic computer and is dedicated to multiplication. Herein, the term "multiplication" means deriving a partial product of a multiplicand and each part (one or more bits) of a multiplier and adding the derived partial products to one another.
The multiplication is built as a standard function in the recent computer. To improve the operating performance, several kinds of methods have been developed. As one method for enhancing the operating performance (speed), the Booth algorithm can be used. The Booth algorithm is arranged to reduce the number of units for producing a partial product and make the arrangement of each unit simpler. As another method, the Wallace tree can be used. The Wallace tree uses a tree for making the additions of partial products as parallel as possible, thereby reducing the necessary adding time.
As another method for a very large scale integrated circuit (VLSI), a method has been used where the used fundamental circuits are arranged in a two-dimensional regular array format. A so-called array multiplier corresponds to a multiplier using this method.
However, all of the above-mentioned multiplying methods have a disadvantage in that they cannot theoretically yield a long enough time margin to rapidly and stably perform a multiplication.
Furthermore, those serial or parallel multiplication methods have a disadvantage in that they cannot be used for both of a binary signal and a quadruple signal and cannot perform a rapid multiplication.